VIPUL BHATNAGAR et al: ANALYSIS OF SRAM BIT CELL TOPOLOGIES IN SUBMICRON CMOS
نویسندگان
چکیده
The paper investigates on the design aspects of different SRAM cells for access time, power consumption and static noise margin. All the designs are made by using standard 90nm CMOS process. Simulations have been done for 6T, 7T, 9T and 10T SRAM cells. 10T SRAM cell shows the best SNM among all the simulated cells. 9T shows least power and least access time. 6T cells stability limits the potential power saving achievable by voltage scaling while proposed 9T cells enhance stability. Layouts are also being made to create as compact a cell as possible. The results are compared with the actual known results and have been found justified.
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